1. Field of the Invention
The present invention is related to Integrated circuit (IC) chip packaging and, more particularly, to high signal density IC chip packaging for packaging single or multiple ICs in a single module and the method of manufacture thereof.
2. Background Description
Performance and signal density demands are forcing Single chip modules (SCMs) and, especially, multi-chip modules (MCMs) to become more and more complex. Ceramic module signal density is being increased by increasing the number of ceramic wiring layers (with one wiring or power layer on each ceramic layer). However, increasing signal density, increases signal load capacitance and impairs chip performance.
Thin film (TF) wiring layers on ceramic substrates have increased module wiring density and improved signal transmission characteristics, while dramatically reducing the number of ceramic layers. However, these modules require reference voltage layers for noise reduction and, when required, for impedance matching.
Typically, these ceramic modules include at least two TF layers for defining capture pads, a ground plane layer, and wiring layer. Unfortunately, these TF processes adapted for making such a module are very expensive because they require a planar ceramic substrate surface.
Thus, new cost effective methods are needed to reduce the TF ceramic fabrication costs.